Spurred by very deep submicron design (VDSM) and complex multi-million gate chips, system-on-a-chip (SOC) technology now engulfs escalating functionality while integrating extremely diverse IP cores. At the same time, these sophisticated SOCs (such as those used in advanced data communications and wireless products) are also generating thorny design and test problems.

In fact, problems for SOC designers are cropping up across the board in manufacturing test, diagnosis, and measurement. Many EDA toolmakers simply ignore these issues, erroneously perceiving them as back-end concerns. Unless these difficult test problems are solved at the front end, there will continue to cause increasing impact on time to market, device quality, and overall IC cost.

According to Dataquest and our own research, high complexity design starts greater than one million gates will catapult from 410 in 1998 to 3,966 in 2003. It's right at this one million-gate threshold, and beyond, that "embedded test" circuitry becomes the most efficient and makes the most economic sense to meet product validation challenges (see Figure 1).

Figure 1 - Big designs on the map

Predications indicate design starts at over 1 million gates, including ASSPs and cell-based ASICs, increasing significantly to meet explosive demand.

Embedded test installs intellectual property (IP) that allows each IC to test itself. The technique integrates the tester functionality ("microtester") into the SOC, taking up only about two to three percent of the silicon die area (see Figure 2).

Embedded test has evolved from two distinct test concepts - external automatic test equipment (ATE) and conventional design-for-test (DFT) technology - and incorporates the high-speed and high-bandwidth portions of external ATE directly into the ICs. When properly implemented, embedded test can solve chip-, board-, and system-level test. It also allows chip designers to speed up diagnosis, debug, and bring up.

Figure 2 - Taking the solution on-board

SOC with an embedded test solution. The actual on-chip function appears in the lower right-hand corner of the IP block.

Beyond helping to solve the design and manufacturing issues, embedded test successfully spans the space across DFT and manufacturing segments, and can even migrate into the realm of remote diagnostics (or remote access). Once an IP core is designed with an embedded microtester, it becomes easier to use and reuse without having to resolve test challenges for each implementation. The same embedded test functionality can also be used and reused throughout the life of the silicon - at wafer probe, burn in, final test, board assembly, system development, field installation, and for ongoing remote diagnosis (see Figure 3).

Test nightmare

The integration of memory, mixed signal, IP cores, and embedded microprocessors into a single SOC is simultaneously a technical marvel and a test nightmare. IC test equipment costs are going sky high, inflated by higher densities, higher capital costs, multi-pass testing, longer test time, and combined function testers. The bottom line? Per-unit test costs are rising more rapidly than any other aspect of IC manufacturing.

Figure 3 - For the long haul

The embedded test spectrum for use and resuse of on-chip test techniques spans the lifetime of a product.

But now there's a major paradigm shift: IC test doesn't have to be difficult or expensive. With the capability to place most test intelligence on-chip, the need for test programs, test vector generation, and transfer will be eliminated. This lessens the complexity of the hand-over from design to manufacturing, while also reducing manufacturing test ramp time and debug from months to weeks.

Embedded test strategies enable remote self-test and diagnosis of any hardware function down to the gate level throughout the lifetime of the IC, as well as for servicing and maintaining products. For example, 3G wireless base stations can be installed more inexpensively and cost effectively anywhere in the world. Beyond wireless applications, other remote, self-diagnostic embedded test applications could include high-end workstations and servers to service Internet infrastructure, and lower-cost, more reliable network switches.

Is there still a need for Ôbig iron' ATE? As gate counts, pin counts, and device speeds go higher, the cost and value of ATE becomes increasingly problematic. Intel has publicly projected that by the year 2003, the company will spend more to test one of its microprocessors than it will to manufacture these complex devices. Traditional external hardware test costs will soar over the next few years, these rapidly rising costs driven by requirements for 2,000-pin devices and 2GHz clock speeds.

Embattled ATE

Traditional external hardware test costs have averaged three to five percent of semiconductor revenue for the past 20 years, but that percentage is destined to escalate dramatically. Although leading ATE manufacturers have always been challenged by lower cost and reduced functionality machines, the real dilemma for the entrenched players will come from the rising acceptance of embedded microtesters.

The rise of microtesters evokes an earlier paradigm shift - mainframe computers to individual PCs. Just as personal computers are ubiquitous today, some day every chip will ship with its own microtester on-board. Microtesters, therefore, offer yet another example of displacement technology.

ATE companies are reaching the physical limits of cost, performance, access, and flexibility. With ATE system price tags moving into the $5 million-plus range, it's obvious that the ATE establishment needs to quickly acknowledge the future directions in their industry or risk being blindsided by emerging test technologies.

Rodger Sykes is vice president of marketing and business development for LogicVision, Inc., (San Jose). Previously he worked in a marketing and development capacity for Philips Semiconductor and, prior to Philips, spent 13 years at Texas Instruments.

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